The present invention relates generally to digital data processing equipment and more specifically to an improved method of correcting memory errors.
A rather well known method for detecting the occurrence of errors in digital data processing and digital transmission systems involves the use of the so-called "parity checking" technique. In general, an addition bit position is assigned to each word of data and that bit is set to a binary "1" or "0" such that the total number of 1-bits in the composite word will be odd or even, depending upon the convention used. Assuming that an odd parity convention is employed, when the word is transmitted from a source to a destination, a check is made to determine whether the number of 1-bits is still odd. If the check reveals that the transmitted word includes an even number of 1-bits, it is known that an error has occurred in the transmission.
For a fuller understanding of parity checking and its application to a magnetic tape storage system, reference is made to the Lisowski U.S. Pat. No. 3,183,483. As is set forth in the Lisowski patent, a higher degree of error checking can be accomplished by not only applying parity checking techniques to individual words, but also by applying the technique to a series of words stored serially on a magnetic tape. This last mentioned technique is the so-called "longitudinal" parity checking. By using both horizontal and longitudinal parity checking, a higher degree of error detection can be accomplished.
While longitudinal parity checking has found application in magnetic tape and punched paper tape devices which are commonly considered peripheral equipment in an electronic data processing system, only horizontal parity checking has found application with the information stored in the main random access memories (RAM's) commonly utilized in computer mainframes.
The present invention utilizes the arrangements for generating longitudinal parity for the data stored in a computer mainframe memory (i.e., RAM) disclosed by Harry Winthrop Moore, III, in U.S. Pat. No. 3,387,901 assigned to the assignee of the present invention. Whereas Moore III teaches the generation of longitudinal parity for computer mainframe memories, the present invention combines that technique with the horizontal parity common in the art in a novel fashion to provide an apparatus for and a method of correcting errors from a random access memory.